Multicore systems are being used more in critical avionics systems due to their improved SWaP characteristics, increasing need for performance, and decreasing availability of single core processors. In recent years, airworthiness guidance for multicore DO-178C software were outlined in CAST-32A and will be made official in the FAA’s upcoming AC 20-193 guidance. This guidance is expected to be significantly similar to EASA’s current AMC 20-193 guidance.

Multicore systems present certification challenges due to the impact of interference from software running on different cores reducing the predictability of behavior of hosted applications. This includes both timing behavior and software data coupling and control coupling. Identifying interference channels and verifying a system’s ability to operate reliably given the interference present on the platform form the main thrust of the airworthiness guidance, but what does it take to do this analysis and verification?

In this presentation, we provide some insights to help answer these questions, using anonymized data collected from multicore verification projects we have delivered.

We’ll cover questions including the following:

• Which factors can contribute to platform reliability and reduce downstream verification effort?

• What extra planning activities are required for multicore certification and how can they be made more efficient?

• How many interference channels are on a typical platform and how long does it take to sufficiently analyze each?

• How can you validate the interference present on a platform?

• How can you verify application worst-case execution time on a multicore platform, and what is the overhead of doing so?