An increasingly important trend in the design of real-time and embedded systems is the integration of components with different levels of criticality onto a common hardware platform. At the same time, these platforms are migrating from single cores to multi-cores and, in the future, manycore architectures. Criticality is a designation of the level of assurance against failure needed for a system component.

A mixed criticality system (MCS) is one that has two or more distinct levels (for example safety critical, mission critical and non-critical). Perhaps up to five levels may be identified (see, for example, the IEC 61508, DO-178B,

DO-254 and ISO 26262 standards). In this talk some of the techniques being developed for MCS will be outlined, as will schemes by which the different assuance methods for each criticality level can be exploited to reduce resource usage.