This presentation will discuss and elaborate the purpose and strategic thinking of the MOD/Dstl Edge Avionics with Digital Security by Design technology.

Background:

Secure by Design is the overriding strategic priority of MOD’s Cyber Resilience Strategy for Defence and will be likely in MOD contracts and updated Defence Standards.

As part of Wave 3 Industrial Strategy Challenge, UK Research and Innovation (UKRI, Innovate UK) the Digital Security by Design (DSbD) project delivered secure silicon in the form of a Capability Hardware Enhanced RISC Instructions (CHERI) based Technology Platform Prototype (TPP) called Morello. The Morello TPP is a multicore evaluation board with supporting system software. It is estimated CHERI blocks up to 70% of memory vulnerabilities in the software stack in the Morello hardware by enforcing a formally verified fine grained memory control. The new capability is a potential step change in reducing the attack surface below the software stack.

Integration of priority and technology:

The Edge Avionics with Digital Security by Design concept arose out the opportunity to design a defence related project/demonstrator to exploit the new secure silicon processers using CHERI technology.

Dstl, with industrial partners, is developing a demonstration Avionics architecture using Morello and enhanced aerospace tools and data concentrators to produce an experimental Edge Avionics architecture. This presentation will overview the underpinning technologies; how they are being integrated, development of adapting legacy software, development of new tool technologies and new innovations that generally benefit the high integrity ecosystem.

Depending on how the project has progressed early results from the integration and research program may be shared.